(1) Field of the Invention
The present invention relates to a complementary semiconductor device with a dielectric isolation structure and, more particularly, to an improved method of producing a complementary epitaxial passivated integrated circuit (CEPIC) comprising n-type and p-type islands, each island having an element, such as a transistor, diode, or resistor, and being surrounded with a dielectric layer (e.g., a silicon dioxide (SiO.sub.2) layer) supported with a thick polycrystalline silicon layer.
(2) Description of the Prior Art
A semiconductor device having a dielectric isolation structure is well known from, for example, FIGS. 8-16 and 8-17, Electronics Engineer's Handbook, McGraw-Hill Book Company, 1975, page 8-12. Such a semiconductor device is produced by the steps of; forming a V-shaped groove by anisotropically etching an n-type silicon substrate to form mesa portions; thermally oxidizing the exposed silicon of the substrate to form an oxide layer (i.e., a dielectric layer); depositing a thick, polycrystalline silicon layer on the oxide layer; turning the substrate upside down; lapping the substrate to expose the oxide layer at the bottom of the V-shaped groove and to form isolated n-type single crystalline islands; and forming transistors in the isolated islands, respectively. Each of the islands is completely isolated by surrounding it at the sides and bottom with the oxide layer having a thickness of several micrometers. Therefore, each of the formed transistors can have a very high breakdown voltage. In this case, all the islands are of either the p-type or n-type conductivity.
For the formation of a complementary circuit, however, a semiconductor device having both p-type islands and n-type islands is necessary (for example, cf. T. SAKURAI and K. KATO, IEEE Transactions on Electron Devices, Vol. ED-28, No. 10, pp. 1200-12 01, 1981). Such a device is referred to as a CEPIC.
When a p-type single crystalline substrate is used for p-type islands, for example, the n-type islands are formed as follows. The substrate is selectively etched to form mesa portions for the p-type islands. The mesa portions are covered with an insulating layer of, e.g. silicon dioxide (SiO.sub.2). Silicon is epitaxially grown so as to form an n-type epitaxial single crystalline silicon layer on the exposed surface of the p-type substrate. At the same time, a polycrystalline silicon layer is formed on the insulating layer.
The thickness of the n-type epitaxial layer, corresponding to the height of the p-type mesa portions, is, e.g., approximately 60 .mu.m for formation of a transistor having a breakdown voltage of, e.g., 400 V. In this case, the thickness of the polycrystalline silicon layer above the p-type mesa portions is approximately 85 .mu.m, since the growth rate of the polycrystalline silicon is 1.4 times larger than that of the epitaxial silicon. Accordingly, the difference between the top surface of the polycrystalline silicon layer and that of the epitaxial layer is 85 .mu.m.
Next, a masking layer (e.g., an SiO.sub.2 layer or a dual layer of SiO.sub.2 and Si.sub.2 N.sub.4) is formed on the entire surface of the polycrystalline silicon layer and epitaxial layer. A photoresist layer is applied on the masking layer. The photoresist layer is selectively exposed by using a patterned photomask and is developed, so that the photoresist layer remains above portions of the epitaxial layer corresponding to the n-type islands. The masking layer, except the portion thereof covered with the remaining photoresist layer, is removed. Using the remaining masking layer as a mask, the polycrystalline silicon layer is removed and the epitaxial layer is selectively etched to form the n-type islands.
It is difficult, however, to position the n-type islands at predetermined positions with accuracy and to make them to the exact predetermined dimensions, since a large gap (e.g., 85 .mu.m) exists between the photomask and the photoresist layer on the epitaxial layer, which results in distortion of the developed photoresist images. Therefore, it is difficult to make the CEPIC denser. Furthermore, since the photomask may come into contact with projecting portions of the polycrystalline silicon layer covered with the masking layer and the photoresist layer, the photomask is easily damaged.